SOC Design Verification Engineer

What you'll do

• Develop reusable UVM testbenches, tests, coverage models, and automated regressions; debug issues and manage bugs through resolution.
• Verify low-power design intent using UPF and end-to-end WiFi and Bluetooth traffic flows; apply formal verification where appropriate.
• Collaborate on verification plans and methodology, explore AI-assisted verification, and support post-silicon bring-up as needed.

What they ask for

• Bachelor’s degree.
• Hands-on experience across the verification cycle, including test planning, testbench implementation, test creation and debug, and coverage closure.
• Strong SystemVerilog and Verilog skills, with working knowledge of UVM.
• Constrained-random verification skills and understanding of digital logic design, SOC architecture, and microarchitecture.

Nice to have

• ASIC/SOC experience through tape-out; verification experience with PCIe, bus fabric/NOC, AHB/AXI, WiFi, or Bluetooth.
• Experience with UPF, SVA or formal tools, coverage modeling, embedded CPU verification, C/C++ or assembly, Python or Perl, or AI/ML verification workflows.

Pay

$122,700 and $214,300 (base salary); $129,300 and $225,300 (base salary)

Tools

SystemVerilog, Verilog, UVM, UPF, PCIe, JasperGold, Python, Perl

AI focus

Explore and apply AI-assisted verification techniques to improve team productivity, including potential use in test generation, debug, and coverage closure.