Apple
SOC Design Verification Engineer
$123K–$225K
Irvine, California +2 · Full-time · Posted Oct 27, 2026
- Location
- Irvine, California
San Diego, California
Sunnyvale, California - Education
- Bachelor’s degree required.
About the job
Verifies wireless system-on-chip designs from block through full SOC integration, driving verification planning, implementation, coverage closure, and signoff.
What you'll do
- Develop reusable UVM testbenches, tests, and coverage models; debug issues and manage bugs through resolution.
- Verify low-power design intent and end-to-end WiFi and Bluetooth traffic; support integration and post-silicon bring-up as needed.
- Improve regression and verification methodology, apply formal methods where appropriate, and explore AI-assisted verification.
What they ask for
- Minimum requirement of a bachelors degree.
- Hands-on experience across the verification cycle, including test planning, testbench implementation, test creation and debug, and coverage closure.
- Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
- Problem-solving and debugging skills with constrained-random verification; understanding of digital logic design, SOC architecture, and microarchitecture.
Nice to have
- Experience taking an ASIC/SOC from concept through tape-out; verification experience with PCIe, bus fabric/NOC, or AHB/AXI architectures.
- Wireless SOC, low-power/UPF, SVA or formal tools, coverage modeling, embedded CPU/C/C++/assembly, Python or Perl, or AI/ML verification experience.
Pay
$122,700 and $214,300 USD base salary; $129,300 and $225,300 USD base salary
Tools
SystemVerilog, Verilog, UVM, UPF, PCIe, AHB/AXI, JasperGold, Python
AI focus
Explore and apply AI-assisted verification techniques, including potential use in test generation, debug, and coverage closure.
Model-written summary · the original posting is authoritative