SOC Design Verification Engineer

What you'll do

• Plan and execute pre-silicon RTL verification, building reusable UVM testbenches, tests, coverage models, and automated regression flows through signoff.
• Debug failures, manage bugs, verify low-power intent with UPF, and validate end-to-end WiFi and Bluetooth traffic flows.
• Apply formal and AI-assisted verification where appropriate, contribute to reviews and methodology, and support post-silicon bring-up as needed.

What they ask for

• BS degree and at least 10 years of relevant industry experience.
• Hands-on experience across verification planning, testbench implementation, test creation and debugging, and coverage closure.
• Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
• Problem-solving and constrained-random verification skills; understanding of digital logic design, SOC architecture, and microarchitecture.

Nice to have

• Experience taking an ASIC/SOC from concept through tape-out; wireless SOC, PCIe, bus fabric/NOC, or AHB/AXI verification experience is also valued.
• Experience with UPF, SVA or formal tools, coverage models, embedded CPU verification, C/C++ or assembly, Python or Perl, or AI/ML verification workflows.

Pay

$175,000 and $308,500 (base salary); $184,700 and $324,800 (base salary)

Tools

SystemVerilog, Verilog, UVM, UPF, PCIe, JasperGold, Python, Perl

AI focus

Explore and apply AI-assisted verification techniques, including potential use in test generation, debug, and coverage closure.