Apple
SoC Design Verification Engineer
$185K–$325K
Austin, Texas +1 · Full-time · Posted Oct 27, 2026
- Location
- Austin, Texas
Sunnyvale, California - Experience
- 10+ years required.
- Education
- B.S required; MSEE, MSCS or beyond preferred.
About the job
Verifies Cellular 5G SoCs by developing reusable UVM test environments, coverage-driven plans and infrastructure, and improving verification methodology and tape-out readiness.
What you'll do
- Create verification plans, test benches, sequences, and test infrastructure for IPs and subsystems.
- Integrate reusable UVM environments and verification components at SoC level, targeting coverage and coordinating with design, architecture, software, firmware, and external IP teams.
- Collaborate on verification-flow improvements and deploy new tools and AI/ML methodology.
What they ask for
- Demonstrated knowledge of object-oriented programming principles and experience in an OOP-based language.
- Digital Design experience.
Nice to have
- Hands-on experience developing UVM-based testbenches in SystemVerilog.
- Experience developing DUT reference models and verification using HVL.
Pay
$184,700 and $324,800 (USD base salary range)
Tools
Python, C++, Java, SystemVerilog, UVM, SPI, I2C, UART
AI focus
Develop and deploy AI/ML methodology for SoC verification.
Model-written summary · the original posting is authoritative