Apple
SoC Physical Design Engineer, PnR
$129K–$195K
San Jose, California · Full-time · Posted Apr 15, 2026
- Experience
- 0+ years.
- Education
- Minimum BS.
About the job
Implement and sign off physical design partitions for complex SoCs, from netlist through tapeout.
What you'll do
- Collaborate with logic design teams to understand partition architecture and address physical design early.
- Complete netlist-to-GDS2 implementation while meeting schedule and design goals.
- Perform timing, physical, and electrical verification; resolve design and flow issues and drive signoff closure.
What they ask for
- Basic understanding of logic gates.
Nice to have
- Internship/co-op, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
- Strong teamwork and cross-functional collaboration skills; experience with Verilog, VHDL, Python, Perl, TCL, and/or SPICE.
Pay
$129,300 and $194,700 (base salary range; USD)
Tools
GDS2, Verilog, VHDL, Python, Perl, TCL, SPICE
Model-written summary · the original posting is authoritative