Apple
SoC Physical Design Engineer, PnR
Austin, Texas · Full-time · Posted Jan 16, 2026
- Experience
- 3+ years of relevant industry experience.
- Education
- Minimum BS.
About the job
Leads physical design implementation for chips and IP, from RTL to GDS, while addressing timing, area, and power constraints.
What you'll do
- Own physical design implementation, including PnR, bump/RDL, STA, physical verification, EMIR, and sign-off.
- Collaborate with cross-functional teams on physical architecture and develop methodologies, best-known methods, guidelines, and checklists.
- Serve as the primary technical contact for the focus area and tackle timing closure, area, and power optimization.
What they ask for
- Bachelor’s degree (BS).
- 3+ years of relevant industry experience.
Nice to have
- Partition-level P&R knowledge, including floorplanning, clock and power distribution, timing closure, and physical and electrical verification; knowledge of PD construction and analysis flows.
- Recent deep-submicron tapeouts; experience with large SoCs (>20M gates) above 1 GHz; industry-standard tools; ability to meet stringent schedule and die-size requirements; strong interpersonal skills.
Tools
RTL2GDS, PnR, bump/RDL, STA, EMIR
Model-written summary · the original posting is authoritative