Apple
SoC Physical Design Engineer, PnR
$185K–$325K
San Jose, California · Full-time · Posted Apr 15, 2026
- Experience
- 10+ years of relevant industry experience.
- Education
- Minimum BS; preferred MS in Electrical/Electronics/Computer Engineering or related field.
About the job
Implements and optimizes SoC physical design partitions from netlist through tapeout, including verification and signoff closure.
What you'll do
- Complete netlist-to-GDS2 implementation, meeting schedule and design goals.
- Perform timing, physical, and electrical verification and drive signoff closure.
- Resolve physical design and flow issues and optimize partitions for power, performance, and area.
What they ask for
- Minimum BS degree.
- Knowledge of partition-level P&R implementation, including floorplanning, clock and power distribution, timing closure, and physical and electrical verification.
- Knowledge of physical design construction, analysis flows, and methodology.
- Experience with industry-standard tools and familiarity with SoC issues such as multiple voltage and clock domains and mixed-signal block integration.
Nice to have
- MS in Electrical/Electronics/Computer Engineering or related field.
- Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHZ.
Pay
USD $184,700 to $324,800 base salary
Tools
P&R, GDS2
Model-written summary · the original posting is authoritative