Apple
SoC Physical Design Engineer, PnR
Austin, Texas · Full-time · Posted Aug 8, 2026
- Experience
- 0+ years experience.
- Education
- Minimum BS Degree.
About the job
Implements SoC design partitions from netlist through tapeout, closing timing, physical, and electrical verification requirements.
What you'll do
- Drive physical design considerations early with logic design teams.
- Complete netlist-to-GDS2 implementation to meet schedule and design goals.
- Perform timing, physical, and electrical verification and drive signoff closure.
What they ask for
- Minimum BS Degree.
- Basic understanding of logic gates.
Nice to have
- Internship/co-op, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
- Teamwork and collaboration skills; experience with Verilog, VHDL, Python, Perl, TCL, and/or SPICE.
Tools
GDS2, Verilog, VHDL, Python, Perl, TCL, SPICE, Redhawk
Model-written summary · the original posting is authoritative