Apple
SoC Physical Design Engineer, PnR
Beaverton, Oregon · Full-time · Posted Apr 14, 2026
- Experience
- 0+ years of industry experience; no stated alternatives.
- Education
- Minimum BS; preferred MS in Electrical/Electronics/Computer Engineering or related field.
About the job
Implement and optimize physical design partitions for complex SoCs, from netlist through tapeout, and drive verification and signoff closure.
What you'll do
- Work with logic design teams to shape partition physical design early in the design cycle.
- Complete netlist-to-GDS2 implementation while meeting schedule and design goals.
- Drive timing, physical, and electrical verification, signoff closure, and PPA optimization.
What they ask for
- Minimum BS.
- 0+ years of industry experience.
Nice to have
- MS in Electrical/Electronics/Computer Engineering or a related field.
- Experience with partition-level P&R, floorplanning, timing closure, verification, and large SoC design flows.
Tools
GDS2, PnR, P&R
Model-written summary · the original posting is authoritative