Apple
SoC Physical Design Engineer, PnR
$175K–$308K
Irvine, California +1 · Full-time · Posted Jul 28, 2026
- Location
- Irvine, California
San Diego, California - Experience
- 10+ years of relevant industry experience.
- Education
- Minimum BS; preferred MS in Electrical/Electronics/Computer Engineering or related field.
About the job
Own physical implementation of SoC design partitions from netlist to tapeout, closing signoff and optimizing power, performance, and area.
What you'll do
- Partner with logic design to shape partition architecture and physical design early in the cycle.
- Complete netlist-to-GDS2 implementation and timing, physical, and electrical verification through signoff.
- Resolve physical-design and flow issues and optimize PnR partitions for power, performance, and area.
What they ask for
- Bachelor’s degree and relevant industry experience.
- Partition-level P&R implementation, including floorplanning, clock and power distribution, timing closure, and physical and electrical verification.
- Experience with physical design construction and analysis flows and methodology.
Nice to have
- MS in Electrical/Electronics/Computer Engineering or a related field.
- Experience with large SoCs (>20M gates) at frequencies above 1 GHz, process-related design issues, industry-standard tools, or typical SoC integration challenges.
Pay
$175,000 and $308,500 (base salary range)
Tools
P&R, GDS2, PnR
Model-written summary · the original posting is authoritative