Apple
SoC Physical Design Engineer, PnR
$129K–$195K
San Jose, California · Full-time · Posted Apr 14, 2026
- Experience
- 0+ years.
- Education
- BS minimum.
About the job
Implements SoC design partitions from netlist through tapeout, driving physical design, verification, and signoff closure.
What you'll do
- Collaborate with logic design teams to understand partition architecture and address physical design early.
- Complete netlist-to-GDS2 implementation to meet schedule and design goals.
- Perform timing, physical, and electrical verification; resolve design and flow issues and drive signoff closure.
What they ask for
- Basic understanding of logic gates.
Nice to have
- Internship/co-op, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
- Teamwork and cross-functional collaboration skills; experience with Verilog, VHDL, Python, Perl, TCL, and/or SPICE.
Pay
USD 129,300–194,700 base salary
Tools
GDS2, STA, DRC/LVS, Redhawk, Totem, Voltus, Verilog, VHDL
Model-written summary · the original posting is authoritative