Apple
SoC Physical Design Engineer, STA/Timing
$129K–$195K
Austin, Texas +1 · Full-time · Posted Apr 14, 2026
- Location
- Austin, Texas
San Jose, California - Experience
- 0+ years of industry experience; the posting also requires experience with STA and noise, crosstalk, and/or OCV effects.
- Education
- Minimum Bachelor's degree.
About the job
Implements physical design partitions for complex SoCs from netlist to tapeout, focusing on static timing analysis, timing closure, and timing infrastructure.
What you'll do
- Analyze timing paths, debug constraints, and coordinate logic changes to improve timing.
- Create timing ECOs and implement timing infrastructure, scripts, and analysis methodologies.
- Work with Physical Design and design teams, and produce documentation and guidelines.
What they ask for
- Experience with STA.
- Experience with noise, crosstalk, and/or OCV effects.
Nice to have
- Familiarity with timing of large high-performance SoCs, timing closure, circuit modeling, SPICE models, worst-case corner selection, or ECO techniques.
- Good programming skills with Perl and TCL; strong communication skills.
Pay
$129,300 and $194,700 (base salary range; USD)
Tools
STA, Perl, TCL, SPICE
Model-written summary · the original posting is authoritative