Apple
SoC Physical Design Engineer, STA/Timing
Austin, Texas · Full-time · Posted Apr 16, 2026
- Experience
- 3+ years of relevant industry experience.
- Education
- BS
About the job
Own physical implementation of SoC design partitions from netlist to tapeout, focusing on static timing analysis and timing closure.
What you'll do
- Analyze timing paths, debug constraints, and coordinate logic changes to improve timing.
- Create timing ECOs and implement timing infrastructure for tapeout.
- Develop and maintain analysis scripts, methodologies, documentation, and guidelines.
What they ask for
- BS degree.
- 3+ years of relevant industry experience.
- Experience with large-design STA and/or timing closure.
- Programming skills with Perl and TCL.
Nice to have
- Hands-on STA experience and familiarity with timing closure for large, high-performance SoCs in sub-micron technologies.
- Familiarity with noise, crosstalk, OCV, SPICE models, worst-case corner selection, and ECO techniques.
Tools
Perl, TCL, SPICE
Model-written summary · the original posting is authoritative