Apple
SoC Physical Design Engineer, STA/Timing
$175K–$308K
San Diego, California · Full-time · Posted Apr 16, 2026
- Experience
- 10+ years of relevant industry experience.
- Education
- Minimum BS
About the job
Implements physical design partitions for complex SoCs from netlist to tapeout, focusing on static timing analysis, timing closure, and timing infrastructure.
What you'll do
- Analyze timing paths, debug constraints, and work with design teams on logic changes to improve timing.
- Create timing ECOs for tapeout and maintain scripts and methodologies for analysis and runs.
- Implement timing infrastructure and document guidelines and specifications.
What they ask for
- Bachelor’s degree and 10+ years of relevant industry experience.
- Experience with large-design STA and timing closure.
- Programming skills with Perl and TCL.
Nice to have
- Hands-on STA experience and familiarity with timing in large, high-performance SoCs using sub-micron technologies.
- Knowledge of timing-closure methodologies, noise, crosstalk, OCV, SPICE models, worst-case corners, and ECO techniques.
Pay
$175,000 and $308,500 (base salary)
Tools
Perl, TCL, SPICE
Model-written summary · the original posting is authoritative