Apple
SoC Physical Design Engineer, STA/Timing
$142K–$263K
San Diego, California · Full-time · Posted Apr 16, 2026
- Experience
- 3+ years of relevant industry experience.
- Education
- BS
About the job
Implements physical design partitions for complex SoCs from netlist to tapeout, focusing on static timing analysis (STA), timing closure, and timing infrastructure.
What you'll do
- Analyze timing paths, debug constraints, and work with design teams on logic changes to improve timing.
- Create timing ECOs for tapeout and develop scripts and methodologies for analysis and runs.
- Collaborate with the Physical Design team and create documentation, guidelines, and specifications.
What they ask for
- Bachelor’s degree (BS) and 3+ years of relevant industry experience.
- Experience with large-design STA and timing closure.
- Programming skills with Perl and TCL.
Nice to have
- Hands-on STA experience and familiarity with timing in large, high-performance SoC designs in sub-micron technologies.
- Knowledge of timing-closure methodologies, noise, crosstalk, OCV, SPICE models, worst-case corner selection, and ECO techniques.
Pay
USD $142,300 to $263,300 base salary
Tools
Perl, TCL, SPICE
Model-written summary · the original posting is authoritative