Apple
SoC Physical Design Engineer, STA/Timing
Beaverton, Oregon · Full-time · Posted Apr 15, 2026
- Experience
- 0+ years of experience.
- Education
- Minimum Bachelor's degree.
About the job
Implements physical design partitions for complex SoCs from netlist to tapeout, focusing on static timing analysis, timing closure, and timing infrastructure.
What you'll do
- Analyze timing paths, debug constraints, and work with design teams on logic changes to improve timing.
- Create timing ECOs for tapeout and develop scripts and methodologies for analysis and runs.
- Coordinate with the Physical Design team, implement timing infrastructure, and create documentation and guidelines.
What they ask for
- Experience with STA.
- Experience with noise, crosstalk, and/or OCV effects.
Nice to have
- Familiarity with timing of large high-performance SoC designs, timing closure, circuit modeling, SPICE models, or worst-case corner selection.
- Perl and TCL programming skills; familiarity with ECO techniques and implementation.
Tools
STA, Perl, TCL, SPICE
Model-written summary · the original posting is authoritative