Apple
SoC Physical Design Engineer, STA/Timing
$150K–$278K
San Jose, California · Full-time · Posted Apr 14, 2026
- Experience
- 3+ years of relevant industry experience.
- Education
- Minimum BS
About the job
Implements physical design partitions for complex SoCs from netlist to tapeout, focusing on static timing analysis, timing closure, and timing infrastructure.
What you'll do
- Analyze timing paths and debug constraints with design teams to improve timing.
- Create timing ECOs and implement timing infrastructure for tapeout.
- Maintain analysis scripts and methodologies, and document guidelines and specifications.
What they ask for
- Bachelor’s degree and 3+ years of relevant industry experience.
- Experience with large-design STA and timing closure.
- Programming skills with Perl and TCL.
Nice to have
- Hands-on STA experience and familiarity with timing closure methodologies for large, high-performance SoCs.
- Familiarity with SPICE models, worst-case corner selection, ECO techniques, noise, crosstalk, and OCV effects.
Pay
$150,400 and $277,600 (base salary)
Tools
Perl, TCL, SPICE
Model-written summary · the original posting is authoritative