Apple
SoC Physical Design Engineer, STA/Timing
Beaverton, Oregon · Full-time · Posted Apr 15, 2026
- Experience
- 10+ years of relevant industry experience.
- Education
- Minimum BS.
About the job
Own physical implementation of SoC design partitions from netlist to tapeout, focusing on timing analysis and closure.
What you'll do
- Debug constraints and work with design teams on logic changes to improve timing; analyze timing paths.
- Collaborate with Physical Design and create timing ECOs for tapeout.
- Create and maintain analysis scripts, methodologies, timing infrastructure, documentation, and guidelines.
What they ask for
- Strong programming skills with TCL.
Nice to have
- Experience with large-design STA or Timing Closure, including high-performance SoCs in sub-micron technologies.
- Knowledge of timing effects and modeling, SPICE simulation, ECO techniques, or scripting languages such as Perl or python.
Tools
TCL, Perl, python, SPICE
Model-written summary · the original posting is authoritative