Apple
SoC Physical Design Verification Engineer
$150K–$278K
Austin, Texas +2 · Full-time · Posted May 28, 2026
- Location
- Austin, Texas
Beaverton, Oregon
San Jose, California - Experience
- 3+ years of relevant industry experience.
- Education
- BS
About the job
Performs chip- and block-level physical verification for SoCs and drives signoff closure through tapeout.
What you'll do
- Run physical verification checks, including LVS, DRC, design-for-manufacturing, design-for-yield, and lithography.
- Collaborate with CAD, Technology, and implementation teams to bring up and validate flows and achieve signoff closure.
- Support cross-functional schedules and work on padring, bump, and RDL design with package and floorplan teams.
What they ask for
- BS degree.
- 3+ years of relevant industry experience.
Nice to have
- Experience with physical verification flows, full-chip integration, ESD, macro placement, and digital/analog mixed-signal back-end verification.
- Scripting skills in perl/python/tcl; experience with Mentor Calibre or Synopsys ICV; tapeout signoff experience; layout design experience is a plus.
Pay
USD $150,400 to $277,600 base salary
Tools
LVS, DRC, perl, python, tcl, Mentor Calibre, Synopsys ICV
Model-written summary · the original posting is authoritative