Apple
SoC Physical Design Verification Engineer
$185K–$325K
Austin, Texas +2 · Full-time · Posted May 28, 2026
- Location
- Austin, Texas
Beaverton, Oregon
San Jose, California - Experience
- 10+ years of relevant industry experience.
- Education
- BS
About the job
Performs physical verification for SoCs, collaborates on verification flows and tapeout signoff, and works on padring, bump, and RDL design.
What you'll do
- Perform chip- and block-level checks including LVS, DRC, design-for-manufacturing, design-for-yield, and lithography.
- Collaborate with CAD, Technology, and implementation teams to validate flows and drive signoff closure for tapeout.
- Lead schedules and support cross-functional work on padring, bump, and RDL design with package and floorplan teams.
What they ask for
- BS degree.
- 10+ years of relevant industry experience.
Nice to have
- Experience with physical verification flows, full-chip integration, ESD, macro placement, and digital/analog mixed-signal backend verification.
- Scripting with perl/python/tcl; experience with Mentor Calibre or Synopsys ICV; tapeout signoff record; layout design experience.
Pay
$184,700 and $324,800 (USD base salary)
Tools
LVS, DRC, perl, python, tcl, Mentor Calibre, Synopsys ICV
Model-written summary · the original posting is authoritative