Apple
SoC Physical Design Verification Engineer
$129K–$195K
Beaverton, Oregon +1 · Full-time · Posted May 28, 2026
- Location
- Beaverton, Oregon
San Jose, California - Experience
- 0 years of relevant industry experience required.
- Education
- BS degree.
About the job
Performs chip- and block-level physical verification for SoCs, supports flow validation and tapeout signoff, and works on package-related layout.
What you'll do
- Run physical verification checks, including LVS, DRC, design-for-manufacturing, design-for-yield, and lithography.
- Collaborate with CAD, Technology, and implementation teams to validate flows and drive signoff closure for tapeout.
- Lead schedules and support cross-functional efforts involving padring, bump, and RDL design.
What they ask for
- BS degree.
Nice to have
- Experience with physical verification flows such as DRC/LVS/ANT and layout integration methodology.
- Knowledge of RTL-to-GDS physical design flow, scripting for flow debugging and enhancements, or tools such as Mentor Calibre and Synopsys ICV; layout design experience is a plus.
Pay
$129,300 and $194,700 USD base salary
Tools
LVS, DRC, ANT, Mentor Calibre, Synopsys ICV
Model-written summary · the original posting is authoritative