STA & Custom Logic Design Engineer

What you'll do

• Own custom-design timing closure throughout the project cycle; develop STA constraints and perform block- and chip-level timing and noise analysis.
• Design and characterize transistor- and gate-level custom digital circuits in mixed-signal chips; collaborate on timing changes and design methodologies.
• Support verification and DFT debugging, and assist CAD teams with timing verification and closure flows.

What they ask for

• Bachelor’s degree.
• Solid understanding of timing analysis, including setup/hold calculations, POCV, timing constraints, transistor-level delay characterization, and rise/fall-time balancing.
• Experience with timing analysis and verification in high-speed designs such as SerDes and ADC; in-depth understanding of mixed-signal design techniques.
• Track record delivering silicon IPs with design and verification; proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.

Nice to have

• Master’s degree with 3+ years of relevant industry experience; STA tools such as NanoTime, PrimeTime, or Tempus.
• Analog/mixed-signal circuit design, SRAM design, timing/SDC constraints, noise and cross-talk analysis, or scripting in Python, Tcl, or Perl.

Pay

$129,300 and $225,300 USD (base salary range)

Tools

NanoTime, PrimeTime, Tempus, SPICE, Python, Tcl, Perl, SDC