Apple
STA & Custom Logic Design Engineer
$185K–$325K
Sunnyvale, California · Full-time · Posted Oct 14, 2026
- Experience
- Minimum 10 years relevant industry experience; alternatively, preferred qualification states a Master’s Degree with 8+ years of relevant industry experience.
- Education
- BS; Master’s Degree is preferred.
About the job
Own timing closure and static timing analysis for custom mixed-signal circuits, while designing and characterizing custom digital logic for silicon products.
What you'll do
- Own custom-design timing closure throughout the project cycle; develop STA constraints and perform block- and chip-level timing and noise analysis.
- Design and characterize transistor- and gate-level custom digital circuits; collaborate with RTL, custom design, verification, DFT, and CAD teams on timing and methodology.
- Help debug functional and testing issues and deliver timing views to integration teams.
What they ask for
- BS and a minimum of 10 years of relevant industry experience.
- Solid understanding of timing analysis, including setup/hold, POCV, timing constraints, transistor-level delay characterization, and rise/fall balancing.
- Experience with timing analysis and verification in high-speed designs such as SerDes and ADC; in-depth mixed-signal design knowledge.
- Track record delivering silicon IPs with design and verification; proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.
Nice to have
- Master’s Degree with 8+ years of relevant industry experience; experience with STA tools such as NanoTime, PrimeTime, or Tempus.
- Experience in analog/mixed-signal design, SRAM design, timing/SDC constraints, noise and cross-talk analysis, or scripting with Python, Tcl or Perl.
Pay
$184,700 and $324,800 USD base salary
Tools
NanoTime, PrimeTime, Tempus, SPICE, Python, Tcl, Perl, SDC
Model-written summary · the original posting is authoritative