Apple
STA Engineer
$185K–$325K
Austin, Texas +1 · Full-time · Posted Apr 10, 2026
- Location
- Austin, Texas
Cupertino, California - Experience
- 10 years of experience; posting specifies a bachelor’s degree plus 10 years.
- Education
- Bachelor’s degree
About the job
Own timing closure and verification for Apple SoC blocks and full-chip designs, while developing timing methodologies and coordinating with SOC teams on integration and timing issues.
What you'll do
- Own block-level and full-chip timing closure throughout projects; generate timing constraints.
- Develop and maintain timing verification and closure methodologies and flows.
- Collaborate with SOC and cross-functional teams to resolve complex timing issues and deliver IP.
What they ask for
- Bachelor’s degree and 10 years of experience.
Nice to have
- Strong digital design fundamentals; familiarity with ASIC timing concepts and timing corners, process variations, and signal-integrity issues.
- Proficiency in TCL and Perl; exposure to PrimeTime, synthesis, logic equivalence checks, or Synopsys GCA is a plus or desirable.
Pay
$184,700 to $324,800 USD base salary
Tools
TCL, Perl, Primetime, Synopsys GCA (Galaxy Constraint Analyzer)
Model-written summary · the original posting is authoritative