Apple
Standard Cell Design Methodology & Flow Engineer
$138K–$264K
San Diego, California +1 · Full-time · Posted Oct 20, 2026
- Location
- San Diego, California
Santa Clara, California - Experience
- Minimum 3 years of relevant industry experience; preferred qualification states at least 5+ years in listed areas.
- Education
- BS
About the job
Develop standard-cell design methodologies and flows for processor and library development, coordinating with CAD, foundry, technology, and design teams.
What you'll do
- Plan production flows with the internal CAD team and coordinate with foundries on PDK requirements.
- Implement digital blocks in Verilog/SystemVerilog and verify them using simulation or formal checks.
- Analyze timing, power, and area trends, potentially using machine learning to identify quality issues in large datasets.
What they ask for
- BS degree.
- At least 3 years of relevant industry experience.
Nice to have
- 5+ years in library characterization, timing/power/noise/variation modeling, Liberty formats, Spice simulation, or static timing and power analysis flows.
- Experience with timing modeling of custom macros or complex sequential flops; exposure to DFT/scan and DFT-friendly RTL.
Pay
$137,500 and $250,700 USD base salary; $144,600 and $263,800 USD base salary
Tools
Verilog, SystemVerilog, Python, TCL, Perl, VHDL, Spice
AI focus
Use data analysis techniques and/or machine learning models to study circuit trends in timing, power, and area and potentially detect quality issues in large datasets.
Model-written summary · the original posting is authoritative