Apple
Standard Cell Design Methodology & Flow Engineer
$167K–$312K
San Diego, California +1 · Full-time · Posted Aug 20, 2026
- Location
- San Diego, California
Santa Clara, California - Experience
- Minimum 10 years of relevant industry experience; preferred qualification states at least 5+ years in listed specialization areas.
- Education
- BS
About the job
Develop standard-cell design methodologies and flows for processor and library design, collaborating across CAD, foundry, technology, and design teams.
What you'll do
- Plan production flows with internal CAD and coordinate PDK requirements with foundries.
- Collaborate on process requirements and enable tools and flows for design teams.
- Implement digital blocks in Verilog/SystemVerilog, verify them, and analyze circuit data for timing, power, area, and quality trends.
What they ask for
- BS degree.
- At least 10 years of relevant industry experience.
Nice to have
- At least 5 years in library characterization, timing/power/noise/variation modeling, Liberty formats, Spice simulation, or static timing and power analysis flows.
- Experience with custom macro and sequential-flop timing modeling, DFT-friendly RTL, flow automation, data analysis/ML, EDA tools, device physics, or foundry practices.
Pay
USD $166,600 to $296,000 base salary; USD $175,500 to $311,700 base salary
Tools
Verilog/SystemVerilog, Python, TCL, Perl, VHDL, Spice, Liberty Formats
AI focus
Use data analysis techniques and/or Machine Learning models to study timing, power, and area trends and potentially detect quality issues in large datasets.
Model-written summary · the original posting is authoritative