Apple
Timing Design Engineer
Austin, Texas · Full-time · Posted Nov 11, 2025
- Experience
- Minimum 10 years of proven experience; preferred qualifications mention at least 2+ years of experience in writing ASIC timing constraints and timing closure.
- Education
- BS degree in a technical discipline.
About the job
Own SoC timing sign-off and develop timing constraints and sign-off flows to support timing closure across IP and blocks.
What you'll do
- Perform timing sign-off and develop STA and sign-off flows.
- Own IP- and block-level timing constraints from synthesis through sign-off, including custom requirements.
- Collaborate with RTL, CAD, and physical design teams to verify constraints and close timing.
What they ask for
- BS degree in a technical discipline.
- Minimum 10 years of proven experience.
Nice to have
- Detailed knowledge of ASIC timing-closure flow and methodology; ideally 2+ years writing ASIC timing constraints and doing timing closure.
- Primetime and STA flow expertise; knowledge of timing corners/modes, process variations, and signal integrity; hands-on SDC work; Tcl and Perl; familiarity with synthesis, DFT, and backend methods and tools.
Tools
Primetime, Tcl, Perl, SDC
Model-written summary · the original posting is authoritative