Apple
Timing Design Engineer
$185K–$325K
Cupertino, California · Full-time · Posted Nov 11, 2025
- Experience
- Minimum 10 years of relevant experience; preferred qualification also specifies 2+ years of experience in writing ASIC timing constraints and timing closure.
- Education
- BS degree in a technical discipline.
About the job
Own SoC timing sign-off and develop timing constraints and analysis flows to support timing closure.
What you'll do
- Perform timing sign-off and develop STA and sign-off flows.
- Own IP- and block-level timing constraints from synthesis through sign-off, including custom requirements.
- Work with RTL, CAD, and physical design teams to verify constraints and close timing.
What they ask for
- BS degree in a technical discipline.
- Minimum 10 years of relevant experience.
Nice to have
- Knowledge of ASIC timing closure methodology; 2+ years writing ASIC timing constraints and performing timing closure.
- Experience with PrimeTime, timing corners and modes, process variation, signal integrity, Tcl and Perl; familiarity with synthesis, DFT, and backend tools.
Pay
USD $184,700 and $324,800 (base salary)
Tools
Primetime, Tcl, Perl, SDC
Model-written summary · the original posting is authoritative