Apple
Timing Design Engineer
$116K–$203K
Waltham, Massachusetts · Full-time · Posted Apr 20, 2026
- Experience
- 2+ years of experience in writing ASIC timing constraints and timing closure.
- Education
- Bachelor of Science in Electrical Engineering.
About the job
Develop and sign off SoC timing constraints and analysis flows, collaborating across design teams to achieve timing closure.
What you'll do
- Perform timing sign-off and develop STA and sign-off flows.
- Own IP- and block-level timing constraints from synthesis through sign-off, including regular and custom requirements.
- Verify timing constraints and improve constraints and flows to support timing closure and address analysis pessimism or failures.
What they ask for
- Bachelor of Science in Electrical Engineering.
- Knowledge of ASIC timing closure flow and methodology.
- Experience with ASIC timing constraints and timing closure.
- Expertise with STA tools and flow; knowledge of timing corners/modes, process variations, and signal integrity issues.
Nice to have
- Hands-on experience generating and managing timing/SDC constraints.
- Proficiency in Tcl and Perl; familiarity with synthesis, DFT, and backend methodology and tools.
Pay
$116,400 and $203,000 USD base salary
Tools
Primetime, Tcl, Perl, SDC
Model-written summary · the original posting is authoritative