Apple
Timing Design Engineer
Austin, Texas · Full-time · Posted Apr 20, 2026
- Experience
- 2+ years of experience in writing ASIC timing constraints and timing closure.
- Education
- Bachelor of Science in Electrical Engineering.
About the job
Develop and sign off SoC timing constraints and analysis flows, collaborating with RTL, CAD, and physical design teams to achieve timing closure.
What you'll do
- Perform timing sign-off and develop static timing analysis (STA) and sign-off flows.
- Own IP- and block-level timing constraints from synthesis through sign-off, including custom requirements.
- Verify timing constraints and improve constraints and flows to support timing closure and address analysis pessimism or failures.
What they ask for
- Bachelor of Science in Electrical Engineering.
- Proven knowledge of ASIC design timing-closure flow and methodology.
- At least 2 years of experience writing ASIC timing constraints and performing timing closure.
- Hands-on experience generating and managing timing/SDC constraints.
Nice to have
- Expertise with STA tools and flow, timing corners/modes, process variations, and signal-integrity issues; scripting proficiency in Tcl and Perl.
- Familiarity with synthesis, DFT, and backend methodologies and tools; strong communication skills.
Tools
Primetime, Tcl, Perl, SDC
Model-written summary · the original posting is authoritative