Apple
Timing Design Engineer
Beaverton, Oregon · Full-time · Posted Apr 20, 2026
- Experience
- 2+ years of experience in writing ASIC timing constraints and timing closure.
- Education
- Bachelor of Science in Electrical Engineering.
About the job
Own and improve timing constraints, static timing analysis (STA), and sign-off flows for SoC and ASIC designs, collaborating across design and implementation teams to achieve timing closure.
What you'll do
- Perform timing sign-off and develop STA and sign-off flows.
- Own IP- and block-level timing constraints from synthesis through sign-off, including custom requirements.
- Work with RTL, CAD, and physical design teams to verify constraints and close timing.
What they ask for
- Bachelor of Science in Electrical Engineering.
- Proven knowledge of ASIC timing-closure flow and methodology.
- Experience writing ASIC timing constraints and achieving timing closure.
- Expertise with STA tools and flow, timing corners and modes, process variations, and signal-integrity issues.
Nice to have
- Hands-on experience generating and managing timing/SDC constraints; proficiency in Tcl and Perl.
- Familiarity with synthesis, DFT, and backend methodology and tools.
Tools
Primetime, Tcl, Perl, SDC
Model-written summary · the original posting is authoritative