Apple
Timing Design Engineer
Beaverton, Oregon · Full-time · Posted Jan 22, 2026
- Experience
- Minimum 10 years of proven experience; preferred qualification mentions at least 2+ years in ASIC timing constraints and timing closure.
- Education
- BS degree in a technical discipline.
About the job
Own SoC timing sign-off and develop timing constraints and analysis flows to support timing closure.
What you'll do
- Perform timing sign-off and develop STA and sign-off flows.
- Own IP- and block-level timing constraints from synthesis through sign-off, including custom requirements.
- Collaborate with RTL, CAD, and physical design teams; verify constraints and improve flows to address timing-analysis pessimism or failures.
What they ask for
- BS degree in a technical discipline.
- Minimum 10 years of proven experience.
Nice to have
- Detailed knowledge of ASIC timing-closure flow and methodology; 2+ years of experience writing ASIC timing constraints and closing timing.
- Experience with PrimeTime, timing corners/modes, process variation, signal integrity, SDC management, Tcl and Perl, and familiarity with synthesis, DFT, and backend methodology and tools.
Tools
Primetime, Tcl, Perl, SDC
Model-written summary · the original posting is authoritative