Apple
Timing Design Engineer
$175K–$308K
San Diego, California · Full-time · Posted Jan 22, 2026
- Experience
- Minimum 10 years of meaningful experience; preferred qualification also states at least 5+ years in ASIC timing constraints and timing closure.
- Education
- BS degree in a technical discipline.
About the job
Own ASIC/SoC timing sign-off and constraints, developing timing-analysis flows and collaborating with RTL, CAD, and physical design teams to achieve timing closure for PHY designs.
What you'll do
- Perform timing sign-off and develop STA/sign-off flows and IP- and block-level timing constraints.
- Work with RTL, CAD, and physical design teams to understand design intent, develop flows, and close timing.
- Verify timing constraints and improve constraints and flows to address timing-analysis pessimism or failures.
What they ask for
- BS degree in a technical discipline.
- Thorough knowledge of ASIC design timing-closure flow and methodology.
- At least 5+ years of experience in writing ASIC timing constraints and timing closure (preferred qualification).
- Expertise in STA tools and flow, including Primetime (preferred qualification).
Nice to have
- Knowledge of timing corners/modes, process variations, and signal-integrity issues; hands-on timing/SDC constraint generation and management.
- Proficiency in Tcl and Perl; familiarity with synthesis, DFT, and backend methodology and tools.
Pay
$175,000 and $308,500 (base salary range)
Tools
Primetime, Tcl, Perl, STA, SDC
Model-written summary · the original posting is authoritative