Apple
Timing Design Engineer
$123K–$214K
San Diego, California · Full-time · Posted Apr 20, 2026
- Experience
- 2+ years of experience in writing ASIC timing constraints and timing closure.
- Education
- Bachelor of Science in Electrical Engineering.
About the job
Own SoC timing design activities, including timing sign-off, constraint and flow development, and collaboration to achieve timing closure.
What you'll do
- Perform timing sign-off and develop STA and sign-off flows.
- Own IP- and block-level timing constraints from synthesis through sign-off, including regular and custom requirements.
- Work with RTL, CAD, and physical design teams to verify constraints, close timing, and address timing-analysis pessimism or failures.
What they ask for
- Bachelor of Science in Electrical Engineering.
- 2+ years of experience writing ASIC timing constraints and performing timing closure.
- Expertise with STA tools (Primetime) and flow, timing corners/modes, process variations, and signal-integrity issues.
- Hands-on experience generating and managing timing/SDC constraints.
Nice to have
- Proficiency in Tcl and Perl.
- Familiarity with synthesis, DFT, and backend methodology and tools.
Pay
$122,700 and $214,300 (USD, base salary range)
Tools
Primetime, Tcl, Perl, SDC
Model-written summary · the original posting is authoritative