Apple
Wireless Design Verification Engineer
$166K–$325K
San Francisco Bay Area, California +2 · Full-time · Posted Oct 23, 2025
- Location
- San Francisco Bay Area, California
San Diego, California
Waltham, Massachusetts - Experience
- Minimum 10 years of relevant industry experience; preferred qualification includes 7+ years of verification experience of wireless/wired communication block/subsystem.
- Education
- BS
About the job
Performs pre-silicon RTL verification of wireless MAC subsystems and SoC interfaces, developing reusable test benches and coverage-driven tests to ensure design quality.
What you'll do
- Review MAC microarchitecture and specifications; create and refine verification plans to meet coverage targets.
- Build reusable test benches and UVM libraries; develop, run, debug, and analyze directed and constrained-random tests and coverage.
- Use machine learning and AI to identify design and test-bench issues; support validation using Palladium and/or FPGA.
What they ask for
- BS degree.
- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
- Knowledge and experience with ASIC verification flows, including test-bench development, constrained-random testing, and code/functional coverage.
Nice to have
- Verification experience with wireless/wired communication blocks or subsystems; knowledge of protocols such as Bluetooth, UWB, WLAN, or Zigbee.
- Experience using AI technologies in data mining/analysis and Palladium/FPGA validation.
Pay
$175,000 and $308,500 USD base salary; $165,800 and $292,400 USD base salary; $184,700 and $324,800 USD base salary
Tools
Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Palladium, FPGA, Python, Perl
AI focus
Use machine learning and AI technologies to identify design and test-bench issues and ensure DV quality.
Model-written summary · the original posting is authoritative