Apple
Wireless Design Verification Engineer
$123K–$225K
San Francisco Bay Area, California +1 · Full-time · Posted Jul 15, 2026
- Location
- San Francisco Bay Area, California
San Diego, California - Experience
- 3+ years of verification experience of wireless/wired communication block/subsystem (preferred).
- Education
- Bachelor's degree.
About the job
Performs pre-silicon RTL verification of wireless MAC subsystems and their SoC interfaces, developing reusable verification environments and driving design-quality closure.
What you'll do
- Create and refine verification plans, reusable testbenches, UVM libraries, and coverage models.
- Develop and run directed and constrained-random tests; debug failures, track bugs, and work with designers to resolve issues.
- Apply machine learning and AI to identify design and testbench issues, and support subsystem validation using Palladium and/or FPGA.
What they ask for
- Bachelor's degree.
- Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
- Knowledge and experience of ASIC verification flows, including testbench development, constrained-random testing, and code/functional coverage.
Nice to have
- Verification experience with communication blocks/subsystems or components such as MAC, PHY, DMA, timer, AMBA bus and fabric, or encryption/decryption engine.
- Knowledge of Bluetooth, UWB, WLAN, or Zigbee; scripting in shell, Python, or Perl; AI data mining/analysis; or Palladium/FPGA validation.
Pay
$122,700 and $214,300 (base salary); $129,300 and $225,300 (base salary)
Tools
Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Palladium, FPGA, Python, Perl
AI focus
Use machine learning and AI technologies to identify design and testbench issues and ensure DV quality; experience using AI technologies in data mining/analysis is preferred.
Model-written summary · the original posting is authoritative