Wireless MAC Design Verification Engineer

What you'll do

• Create verification plans, reusable UVM test benches, and directed and constrained-random tests; debug failures and drive issue closure.
• Develop and analyze coverage models, adding tests to meet coverage targets and improve design quality.
• Use machine learning and AI to identify design and test-bench issues, and support MAC validation with Palladium and/or FPGA.

What they ask for

• BS and a minimum of 10 years of relevant industry experience.
• Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertion.
• Experience with ASIC verification flows, including test-bench development, constrained-random testing, and code/functional coverage.
• Verification experience in at least one of: MAC, PHY, DMA, timer, AMBA bus and fabric, or encryption/decryption engine.

Nice to have

• 7+ years of verification experience of wireless/wired communication block/subsystem; knowledge of Bluetooth, UWB, WLAN, or Zigbee protocols.
• Proficiency in shell and Python scripting or Perl; experience using AI for data mining/analysis or Palladium/FPGA validation.

Pay

$175,000 and $308,500 USD base salary; $184,700 and $324,800 USD base salary; $165,800 and $292,400 USD base salary

Tools

Verilog, SystemVerilog, UVM, SystemVerilog Assertion, Palladium, FPGA, shell, Python

AI focus

Use machine learning and AI technologies to identify design and test-bench issues and ensure verification quality.