Architect Labs
Member of Technical Staff - Formal Methods
Palo Alto · On-site · Staff · Full-time · Posted May 13, 2026
- Education
- PhD in Computer Science, EECS, or a closely related field, with a dissertation or equivalent body of work in formal methods applied to hardware or systems; exceptional candidates with a BS/MS and a strong industrial track record in formal verification will be considered.
About the job
Build and own the formal-methods stack that verifies AI-generated hardware artifacts for production-grade custom chips.
What you'll do
- Design the formal specification language and intermediate representation across hardware specifications, testbenches, assertions, and RTL.
- Develop proof-obligation generation and integrate SMT solvers, model checkers, and proof assistants to discharge claims.
- Establish soundness arguments and coverage-adequacy methods, collaborating with verification and ML teams.
What they ask for
- PhD in Computer Science, EECS, or a closely related field, with formal-methods work in hardware or systems; exceptional candidates with a BS/MS and strong industrial formal-verification track record may be considered.
- Deep expertise in at least two of temporal logic and model checking, SMT-based verification, refinement-based specification, or proof assistants applied to hardware, distributed, concurrent, or low-level systems.
- Demonstrated application of formal methods to a real artifact that shipped.
- Strong software engineering skills, including building toolchains and integrating formal tools into automated pipelines.
Nice to have
- Industrial formal-verification experience at leading silicon companies, automated reasoning groups, or specialized formal-methods firms.
- Experience with HLS tools, compiler/IR design, or DSL implementation; publications, AI/ML systems familiarity, and early startup experience are also listed as bonuses.
Tools
SMT solvers, TLA+, Lean, Coq, HLS (High-Level Synthesis), RTL
AI focus
The formal layer serves as an oracle for an AI agent loop that optimizes generated hardware artifacts; the role co-designs this layer with ML research teams and supports verification of AI-generated hardware.
Model-written summary · the original posting is authoritative