Architect Labs
Member of Technical Staff - Formal Verification
Palo Alto · On-site · Staff · Full-time · Posted Aug 17, 2026
- Education
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the job
Own formal verification of AI-generated chip design artifacts from specification through tape-out, working with designers and AI teams to prove hardware behavior and integrate verification into AI-driven design flows.
What you'll do
- Develop verification plans, properties, environments, and Spec-to-SVA flows for hardware blocks and subsystems.
- Drive proofs to completion; debug counterexamples, assess coverage and completeness, and document results and open issues.
- Build reusable verification components and automate regressions, result tracking, and failure triage.
What they ask for
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Strong SystemVerilog and SVA skills, including reading complex RTL and writing behavior-accurate properties.
- Hands-on experience with formal verification tools and proof techniques, including model checking, induction, abstraction, and assume-guarantee reasoning.
- Strong scripting skills in Python, Tcl, or similar languages.
Nice to have
- Formal verification sign-off experience for blocks or subsystems in a shipped chip.
- Experience with AI accelerators, processor cores, cache coherence, memory systems, interconnects, UVM, or AI-generated RTL.
Tools
SystemVerilog, SVA, Cadence Jasper, Synopsys VC Formal, Siemens Questa Formal, Python, Tcl, UVM
AI focus
Verifies AI-generated chip designs and collaborates with AI researchers to build Spec-to-SVA flows and integrate formal checks into AI-driven design and repair workflows.
Model-written summary · the original posting is authoritative