Architect Labs
Member of Technical Staff - Microarchitect / RTL Design
Palo Alto +1 · On-site · Staff · Full-time · Posted Apr 16, 2026
- Location
- Palo Alto
Bangalore, India - Experience
- 5+ years; 10+ preferred. At least one advanced-node tapeout experience.
- Education
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
About the job
Own AI-driven microarchitecture and frontend RTL design for production SoC blocks, refining specifications and closing the design loop with implementation feedback.
What you'll do
- Own end-to-end RTL design flow, including code generation and feedback from lint, CDC, synthesis, and timing closure.
- Refine microarchitectural specifications, interface definitions, and area/timing/power trade-offs with the principal architect.
- Maintain design automation and regression infrastructure; support verification and Xilinx FPGA prototyping.
What they ask for
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- 5+ years in RTL design and at least one advanced-node tapeout experience, with work on specialized hardware accelerators.
- Strong SystemVerilog and Python skills; experience with block-level compute datapaths and data movement.
- Experience taking a block from RTL through synthesis and working with physical-design teams on timing, area, and power closure.
Nice to have
- 10+ years of RTL design experience.
- Low-power design, Xilinx FPGA prototyping, SIMD/VLIW pipelines, SVA and functional coverage, or IP delivery experience.
Tools
SystemVerilog, Python, AXI, AXI-Stream, AHB, APB, Xilinx Vivado/Vitis, UPF
AI focus
Own an AI-driven RTL design flow, incorporate implementation feedback into the design loop, and help improve the lab’s in-house AI flow.
Model-written summary · the original posting is authoritative