Architect Labs
Member of Technical Staff - Microarchitectural Validation
Palo Alto · On-site · Staff · Full-time · Posted Aug 3, 2026
- Experience
- 5+ years; 10+ preferred. End-to-end silicon delivery is a strong plus.
- Education
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
About the job
Own verification strategy and validation flows for AI-generated SoC designs, applying hardware verification expertise to AI-driven design automation.
What you'll do
- Review test plans and validation strategies for SoC projects, and advise AI/ML teams on checks, coverage, and interface protocols.
- Define and coordinate verification, validation, and integration flows across IPs, including checkpoints and handoffs.
- Collaborate on simulation- and emulation-ready collateral and track developments in semiconductor verification and AI-driven design automation.
What they ask for
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- 5+ years working on advanced-node tapeouts at top chip companies or fast-moving silicon startups.
- Deep verification and validation expertise, including emulation, architectural and system-level verification, and reusable validation collateral.
- Strong SystemVerilog, UVM, and C/C++ skills; hands-on experience with simulation and emulation flows and at least one listed subsystem area.
Nice to have
- 10+ years of tapeout experience; end-to-end silicon delivery is a strong plus.
- Python; FPGA prototyping; SoC-level DV; or deep AMBA/ACE experience.
Tools
SystemVerilog, UVM, C/C++, Python, APB, AHB, AXI, ACE
AI focus
Provides verification and validation expertise to AI/ML teams and supports AI-driven design automation and AI-generated chip designs.
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