Architect Labs
Member of Technical Staff - Physical Design
Palo Alto · On-site · Staff · Full-time · Posted Sep 14, 2026
- Experience
- Multiple production tapeouts; no number of years stated.
About the job
Build and lead Architect Labs’ physical design function, taking custom AI chips from netlist through physical implementation and signoff to tapeout-ready GDS.
What you'll do
- Establish and qualify the netlist-to-GDS methodology, including tools, constraints, automation, and regression infrastructure.
- Lead block and full-chip implementation and signoff, including floorplanning, placement, routing, timing, and physical checks.
- Work with AI researchers and external partners to improve implementation flows, resolve technical challenges, and build the team.
What they ask for
- Multiple production tapeouts with direct physical implementation and signoff responsibility at 3nm or 2nm, including full-chip closure leadership.
- Experience building production physical design methodology from scratch for advanced nodes.
- Deep expertise in hierarchical implementation, timing analysis, clocking, congestion, low-power design, extraction, and power integrity.
- Recent hands-on mastery of Synopsys Fusion Compiler/ICC2 or Cadence Innovus; strong Tcl and Python skills.
Nice to have
- Direct 2nm methodology bring-up and tapeout experience, including GAA/nanosheet implementation.
- Experience with high-performance processors or accelerators, design-technology co-optimization, chiplets, multi-die integration, or backside power delivery.
Tools
Synopsys Fusion Compiler/ICC2, Cadence Innovus, Tcl, Python
AI focus
Translate physical design expertise into automated flows, structured tool feedback, and evaluations; feed post-route results into architecture, RTL, and the AI system.
Model-written summary · the original posting is authoritative