Microarchitect / RTL Design - Interconnect & Fabric

What you'll do

• Design NoC routers, interconnect fabrics, protocol bridges, and peer-to-peer data-transfer engines; take RTL through lint, CDC, synthesis, and timing closure.
• Define fabric interfaces and specifications, and collaborate with architecture, verification, software, and ML teams on design trade-offs, validation, and improvements to the AI-driven design flow.
• Build RTL automation and regression infrastructure, and support FPGA prototyping and performance characterization.

What they ask for

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
• 5+ years in RTL design and at least one advanced-node tapeout involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems.
• Hands-on AMBA protocol and NoC/fabric design experience, including interconnects, arbitration, flow control, and QoS.
• Experience with high-speed I/O integration, peer-to-peer DMA, synthesizable SystemVerilog, SoC implementation methodology, Python, and PPA closure.

Nice to have

• 10+ years of RTL design experience.
• Experience with coherent multi-chip interconnects, hardware coherence, NoC research, FPGA prototyping, SVA, performance modeling, or related IP delivery.

Tools

SystemVerilog, Python, AMBA AXI4/AXI5, ACE/ACE-Lite, CHI, PCIe, CXL, UCIe

AI focus

Own AI-driven microarchitecture and RTL design, use an AI-driven design flow, and work with software and ML teams to improve the in-house AI flow for traffic modeling and fabric configuration optimization.