Architect Labs
Microarchitect / RTL Design - Memory Subsystem
Palo Alto · On-site · Full-time · Posted Aug 12, 2026
- Experience
- 5+ years; 10+ preferred. At least one advanced-node tapeout involving memory subsystems is required.
- Education
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
About the job
Own the AI-driven microarchitecture and RTL design of production-silicon memory subsystems for ML workloads, from controller design through implementation and closure.
What you'll do
- Design memory controllers, hierarchy components, and memory-side accelerators; define block-level microarchitecture and interfaces.
- Take memory RTL through code generation, lint, CDC, synthesis, timing closure, and FPGA prototyping.
- Collaborate with architecture, DV, software, and ML teams to refine specifications, verification, and the AI-driven design flow.
What they ask for
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
- At least 5 years of RTL design experience and at least one advanced-node tapeout involving memory subsystems.
- Deep familiarity with JEDEC memory standards and hands-on memory-controller design experience.
- Strong SystemVerilog and Python skills, plus experience with memory hierarchy, SoC methodology, and PPA closure.
Nice to have
- 10+ years of experience.
- Experience with HBM integration, CXL, near-memory/PIM design, FPGA prototyping, SVA, memory-system simulation, or related IP delivery and research.
Tools
SystemVerilog, Python, DDR5, LPDDR5X, HBM3, DFI, AXI, Xilinx
AI focus
Design memory subsystems for ML workloads and collaborate with software and ML experts to improve the in-house AI-driven design flow, including workload-driven memory-access optimization.
Model-written summary · the original posting is authoritative