Architect Labs
Vice President of ASIC Engineering
Palo Alto · On-site · Director · Full-time · Posted Oct 29, 2026
About the job
Leads ASIC methodology, teams, and end-to-end delivery of custom AI compute chips from microarchitecture and RTL through tapeout, while building faster, AI-native development workflows.
What you'll do
- Own ASIC methodology and end-to-end chip delivery, including verification, physical design, signoff, and tapeout.
- Develop automation- and AI-enabled workflows to accelerate design, verification, closure, and engineering productivity.
- Lead and grow the silicon engineering team, set quality and PPA standards, and drive key technical and execution decisions.
What they ask for
- Directly led multiple complex, production-volume ASIC or SoC programs through repeated tapeouts.
- Deep expertise across RTL, functional verification, synthesis, timing closure, physical implementation, DFT, signoff, and silicon bring-up.
- Track record of transforming design flows through automation, ML/AI-assisted EDA, verification productivity, or scalable engineering infrastructure.
- Demonstrated delivery of demanding programs, strong first-silicon outcomes, and recruiting and leading high-performing engineering teams.
Nice to have
- Experience with advanced process nodes.
Tools
ASIC, SoC, RTL, DFT, ML/AI-assisted EDA
AI focus
Build an AI-native chip-development flow using automation, intelligent agents, and data-driven feedback loops; improve design iteration, verification, closure, and engineering productivity.
Model-written summary · the original posting is authoritative