Arm
Design Verification Engineer - Memory Controller IP
$250K–$338K
Austin, Texas · Full-time · Posted Oct 29, 2026
About the job
Develops verification strategies and SystemVerilog/UVM environments to validate Memory Controller IP functionality, performance, and protocol behavior across memory technologies.
What you'll do
- Create verification plans, tests, assertions, coverage models, and scoreboards from architectural specifications.
- Analyze regressions, coverage, waveforms, and logs to debug RTL, testbench, and protocol issues.
- Collaborate with design and verification teams to resolve issues and support verification sign-off.
What they ask for
- Practical ASIC or SoC verification experience using SystemVerilog and UVM, including constrained-random testing, assertions, scoreboards, and functional coverage.
- Ability to create verification plans and translate architectural specifications into tests and verification environments.
- Understanding of memory controller architecture and LPDDR or DDR protocol concepts.
- Ability to debug RTL, testbench, and protocol issues using simulation tools, waveforms, and logs.
Nice to have
- Experience with LPDDR5, LPDDR6, DDR5, DDR6, or other memory technologies.
- Knowledge of DFI interfaces, AMBA protocols, simulation/debug tools, or verification workflow automation.
Pay
$249,900-$338,100 USD per year (base salary)
Tools
SystemVerilog, UVM, LPDDR, DDR, DFI, AXI, ACE, CHI
Model-written summary · the original posting is authoritative