Arm
Principal Design Engineer – High-Speed Interconnect
$250K–$338K
Austin, Texas · Principal · Full-time · Posted Jul 20, 2026
- Experience
- 8+ years; related semiconductor roles are an alternative.
- Education
- Bachelor’s or Master’s degree, or equivalent experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Leads the microarchitecture, RTL development, and integration of high-speed interconnect subsystems across silicon products.
What you'll do
- Develop implementation-ready microarchitecture specifications and synthesizable RTL, and drive subsystems from concept through integration and delivery.
- Collaborate across architecture, verification, performance, firmware, physical design, and implementation teams to meet functionality and performance targets.
- Analyze traffic and buffering needs, lead technical reviews and debugging, improve methodologies, and mentor engineers.
What they ask for
- 8+ years of experience in RTL build, microarchitecture, subsystem integration, or related semiconductor roles.
- Hands-on expertise in SystemVerilog and sophisticated, high-performance digital subsystems.
- Deep understanding of PCIe, CXL, and UALink; experience with interconnects, cache hierarchies, memory systems, and high-speed I/O.
- Bachelor’s or Master’s degree, or equivalent experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Nice to have
- Experience with PCIe Gen6 or later, CXL 2.0 or later, UALink, chiplets, or die-to-die connectivity.
- Knowledge of RAS, IDE, TDISP, security, memory pooling, CXL.cache, CXL.mem, and accelerator connectivity.
Pay
$249,900-$338,100 per year (base salary)
Tools
SystemVerilog, PCIe, CXL, UALink, AXI, CHI, ACE, APB
AI focus
The role does not involve AI work; the posting discusses permitted and prohibited AI use in the recruitment process.
Model-written summary · the original posting is authoritative