Arm
Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
$250K–$338K
Austin, Texas +1 · Principal · Full-time · Posted Oct 27, 2026
- Location
- Austin, Texas
San Diego, California - Experience
- 8+ years in coherency protocols, hierarchical cache design, and system-level coherency architectures; also requires 10+ years in semiconductor architecture, design, or related roles.
- Education
- Bachelor’s or Master’s degree (or equivalent) in Electrical or Computer Engineering.
About the job
Architects high-speed I/O and coherent and non-coherent interconnect subsystems for scalable SoC platforms, from customer requirements and specifications through performance optimization and system integration.
What you'll do
- Architect PCIe, CXL, and UA Link subsystems and define interconnect IP and subsystem roadmaps.
- Lead customer architecture engagements and deliver implementation-ready specifications.
- Collaborate across architecture, performance, power, physical design, software, and platform teams to model and optimize end-to-end systems.
What they ask for
- 8+ years of experience with coherency protocols, hierarchical cache design, and system-level coherency architectures.
- Deep expertise in PCIe, CXL, and UA Link protocols and subsystem topics, including link behavior, transaction flows, ordering, memory expansion/pooling, and host/device integration.
- Track record collaborating with performance, power, and physical design teams on the PCIe, CXL, and UA Link stack.
- Bachelor’s or Master’s degree (or equivalent) in Electrical or Computer Engineering with 10+ years of experience in semiconductor architecture, design, or related roles.
Nice to have
- Ability to thrive in dynamic environments with shifting priorities.
- Track record of delivering complex projects on time and to spec.
Pay
$249,900-$338,100 per year (base salary)
Tools
PCIe, CXL, UA Link, Arm IP
Model-written summary · the original posting is authoritative