Arm
Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
$263K–$355K
San Jose, California · Principal · Full-time · Posted Aug 6, 2026
- Experience
- 8+ years in coherency protocols, hierarchical cache design, and system-level coherency architectures; a Bachelor’s or Master’s degree (or equivalent) plus 10+ years in semiconductor architecture, design, or related roles.
- Education
- Bachelor’s or Master’s degree (or equivalent) in Electrical or Computer Engineering.
About the job
Architects high-speed I/O and coherent or non-coherent interconnect systems for scalable SoC platforms, from customer requirements and specifications through performance optimization.
What you'll do
- Architect PCIe, CXL, and UA Link subsystems and define IP and technology roadmaps.
- Lead customer architecture discussions and produce implementation-ready specifications.
- Collaborate across architecture, performance, power, physical design, software, and firmware teams to integrate and optimize SoC systems.
What they ask for
- 8+ years of experience with coherency protocols, hierarchical cache design, and system-level coherency architectures.
- Deep expertise in PCIe, CXL, and UA Link protocols and subsystem behavior.
- Experience collaborating with performance, power, and physical design teams on the PCIe, CXL, and UA Link stack.
- Strong knowledge of areas such as heterogeneous compute, security, caching, and memory systems; demonstrated communication and leadership skills.
Nice to have
- Ability to thrive in dynamic environments with shifting priorities.
- Track record of delivering complex projects on time and to spec.
Pay
USD $262,700-$355,400 per year, base salary
Tools
PCIe, CXL, UA Link, Arm IP
Model-written summary · the original posting is authoritative