Arm
Principal TPIP/HSIO Engineer
$263K–$355K
San Jose, California +3 · Principal · Full-time · Posted Oct 29, 2026
- Location
- San Jose, California
Austin, Texas
Seattle, Washington
San Diego, California - Experience
- 10+ years in high-speed interface design, validation, or bring-up.
- Education
- Bachelor’s or Master’s in Electrical Engineering or related field.
About the job
Leads pre-silicon quality and silicon-to-simulation correlation for high-speed I/O subsystems, coordinating vendors and internal teams to meet quality targets across SoCs.
What you'll do
- Drive closure on DFX metrics for HSIO blocks, including test coverage, margin analysis, scan coverage, and clock-domain checks.
- Analyze silicon measurements and correlate results with design and simulation data; develop validation methodologies.
- Chair DDR and PCIe TPIP Councils and coordinate quality criteria, test architectures, and vendor deliverables.
What they ask for
- Bachelor’s or Master’s in Electrical Engineering or a related field.
- 10+ years experience in high-speed interface design, validation, or bring-up (DDR, PCIe, SerDes).
- Proven post-silicon characterization experience (BER, margining) and correlation with pre-silicon simulations.
- Strong scripting skills in Python and TCL.
Pay
$262,700-$355,400 per year (base salary)
Tools
DDR, PCIe, eUSB, D2D, SerDes, Python, TCL
Model-written summary · the original posting is authoritative